| SPECIFICATIONS |
| Parameter | Condition | Specification |
| A/D converter type | | Successive approximation |
| ADC resolution | | 16 bits |
| Number of channels | | 8 differential, 16 single-ended Software-selectable |
| Input voltage range | | ±10 V, ±5 V, ±2 V, ±1 V Software-selectable per channel |
| Absolute max input voltage | CHx relative to AGND | ±25 V max (power on)
±15 V max (power off) |
| Input impedance | | 1 G? (power on)
820 O (power off) |
| Input bias current | | ±10 nA |
| Input bandwidth | All input ranges, small signal (–3 dB) | 750 kHz |
| Input capacitance | | 60 pf |
| Max working voltage (signal + common mode) | ±10V range | ±10.2 V max relative to AGND |
| ±5V range | ±10.2 V max relative to AGND |
| ±2V range | ±9.5 V max relative to AGND |
| ±1V range | ±9.0 V max relative to AGND |
| Common mode rejection ratio | (fIN = 60 Hz, all input ranges) | 86 dB |
| Crosstalk | Adjacent differential mode channels, DC to 100 kHz | –75 dB |
| Input coupling | | DC |
| Sampling rate | | 0.0149 Hz to 250 kHz; software-selectable |
| Trigger source | | TRIG |
| Sample clock source | | Internal A/D clock or external A/D clock (AICKI pin) |
| Burst mode | | 4 µs
Software-selectable using the internal A/D clock; always enabled when using the external clock (AICKI pin). |
| Throughput | Software paced | 33 to 4000 S/s typ, system dependent |
| Hardware paced | 250 kS/s max |
| Channel gain queue | Up to 16 elements | Software-selectable range for each channel |
| Warm-up time | | 15 minutes min |
